(1) Technical Field
This invention relates to electronic circuits, and more particularly to low dropout voltage regulator circuits.
(2) Background
A well-known type of voltage regulator circuit is a low-dropout (LDO) regulator, which is a DC linear voltage regulator which can operate with a very small input-output differential voltage and maintain a (substantially) constant output voltage Vout with respect to a varying input voltage Vin. Advantages of an LDO voltage regulator generally include a low minimum operating voltage and high efficiency operation.
FIG. 1 is a circuit diagram of a typical prior art low dropout voltage regulator circuit 100. The main components of the LDO circuit 100 are an error amplifier 102 and a power field effect transistor (FET) 104. The resistance of the FET 104, and thus the amount of input voltage Vin passed across the FET 104 as an output voltage Vout, is determined by a control signal applied to the gate of the FET 104. The term “dropout” refers to the minimum voltage difference ΔV=Vin−Vout across the FET 104 at which an LDO regulator is still active before going into saturation.
In operation, one input of the error amplifier 102 monitors the fraction of Vout determined by the resistor ratio of R1 and R2. The second input to the differential amplifier is a reference voltage Vref from a stable voltage source (e.g., a bandgap reference). If the output voltage Vout varies too much relative to the reference voltage Vref, the drive to the gate of the FET 104 changes to maintain a constant output voltage regardless of voltage excursions at Vin (within the circuit specifications). Filter capacitors Cin and Cout may be provided at the input and the output of the LDO circuit 100, as is known in the art.
FIG. 2 is graph of input versus output voltage for a typical prior art low dropout voltage regulator circuit of the type shown in FIG. 1. Within the specifications of a particular circuit, variations of Vin from a minimum value Vin_min to a maximum value Vin_max result in an essentially constant voltage output Vout (graph line 202) within the output specification range Vout_min to Vout_max. By design, the Vout target is typically in the middle of the output specification range, or is set closer to the lower specification limit Vout_min to allow the use of higher dropout voltage LDO circuits.
One aspect of the LDO circuit 100 shown in FIG. 1 is that, with increasing input voltage Vin, regulating the output voltage Vout to a fixed value results in increasing ΔV (ΔV=Vin−Vout); that is, as shown in FIG. 2, ΔV (graph line 204) increases proportionally with the input voltage Vin. As a result, the power dissipation Pdissipation inside the LDO circuit 100 also increases proportionally with ΔV, since Pdissipation=I×ΔV, where I is the load current. Such increased dissipation in an LDO circuit is undesirable because it may increase thermal management complexity and cost of an electronic system or larger circuit utilizing one or more LDO circuits. Minimizing power dissipation is particularly important when an LDO circuit is integrated into circuitry that already is dissipating large amounts of power and/or where thermal management is difficult, as in enclosed, fanless applications.
Accordingly, there is thus a need for a low dropout voltage regulator circuit having lower power dissipation than conventional LDO regulator circuits. The present invention addresses this need.